View HC3-5560-5_133760.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HC-5560
Data Sheet January 1997 File Number
2887.2
PCM Transcoder
The HC-5560 digital line transcoder provides encoding and decoding of pseudo ternary line code substitution schemes. Unlike other industry standard transcoders, the HC-5560 provides four worldwide compatible mode selectable code substitution schemes, including HDB3 (High Density Bipolar 3), B6ZS, B8ZS (Bipolar with 6 or 8 Zero Substitution) and AMI (Alternate Mark Inversion). The HC-5560 is fabricated in CMOS and operates from a single 5V supply. All inputs and outputs are TTL compatible. Application Note #573, "The HC-5560 Digital Line Transcoder," by D.J. Donovan is available.
Features
* Single 5V Supply . . . . . . . . . . . . . . . . . . . . . . .10mA (Typ) * Mode Selectable Coding Including: - AMI (T1, T1C) - B8ZS (T1) - HDB3 (PCM30) * North American and European Compatibility * Simultaneous Encoding and Decoding * Asynchronous Operation * Loop Back Control * Transmission Error Detection
Ordering Information
PART NUMBER HC3-5560-5 TEMP. RANGE (oC) 0 to 70 PACKAGE 20 Ld PDIP PKG. NO. E20.3
* Alarm Indication Signal * Replaces MJ1440, MJ1471 and TCM2201 Transcoders
Applications
* North American and European PCM Transmission Lines where Pseudo Ternary Line Code Substitution Schemes are Desired * Any Equipment that Interfaces T1, T1C, T2 or PCM30 Lines Including Multiplexers, Channel Service Units, (CSUs) Echo Cancellors, Digital Cross-Connects (DSXs), T1 Compressors, etc. * Related Literature - AN573, The HC-5560 Digital Line Transcoder
Pinout
HC-5560 (PDIP) TOP VIEW
FORCE AIS MODE SELECT 1 NRZ DATA IN CLK ENC MODE SELECT 2 NRZ DATA OUT CLK DEC RESET AIS AIS 1 2 3 4 5 6 7 8 9 20 VDD 19 OUTPUT ENABLE 18 RESET 17 OUT1 16 OUT2 15 BIN 14 LOOP TEST ENABLE 13 AIN 12 CLOCK 11 ERROR
Functional Diagram
MODE 1 SELECT 2 NRZ DATA IN CLK ENC OUTPUT ENABLE TRANSMITTER/ ENCODER VDD VSS
VSS 10
CLOCK OUT 1 OUT 2
LOOP TEST ENABLE AIN BIN FORCE AIS RESET CLK DEC
SWITCH RECEIVER/ DECODER NRZ DATA OUT
ERROR DETECT AIS DETECT
ERROR
RESET AIS
AIS
69
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HC-5560
Absolute Maximum Ratings
Voltage at Any Pin . . . . . . . . . . . . . . . . . . . . GND -0.3V to VDD 0.3V Maximum VDD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . 300o
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 70oC Operating VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 5%
Die Characteristics
Transistor Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4322 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . .119 mils x 133 mils Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+V Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAJI CMOS
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Unless Otherwise Specified, Typical parameters at 25oC, Min-Max parameters are over operating temperature range. VDD = 5V SYMBOL MIN TYP MAX UNITS
PARAMETER STATIC SPECIFICATIONS Quiescent Device Current Operating Device Current OUT1, OUT2 Low (Sink) Current (VOL = 0.4V) All Other Outputs Low (Sink) Current (VOL = 0.8V) All Outputs High (Source) Current (VOH = 4V) Input Low Current Input High Current Input Low Voltage Input High Voltage Input Capacitance
lDD 10 IOL1 IOL2 IOH IIL IIH VlL VlH ClN 2.4 3.2 2 2
100
A mA mA mA mA
10 10 0.8
A A V V
8
pF
Electrical Specifications
Unless Otherwise Specified, Typical parameters at 25oC, Min-Max parameters are over operating temperature range. VDD = 5V SYMBOL FIGURE MIN TYP MAX UNITS
PARAMETER DYNAMIC SPECIFICATIONS CLK ENC, CLK DEC Input Frequency CLK ENC,CLK DEC Rise Time (1.544MHz) Fall Time Rise Time (2.048MHz) Fall Time Rise Time (6.3212MHz) Fall Time Rise Time (8.448MHz) Fall Time
fCL tRCL tFCL tRCL tFCL tRCL tFCL tRCL tFCL 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 10 10 10 10 10 10 5 5
8.5 60 60 40 40 30 30 10 10
MHz ns ns ns ns ns ns ns ns
70
HC-5560
Electrical Specifications
Unless Otherwise Specified, Typical parameters at 25oC, Min-Max parameters are over operating temperature range. VDD = 5V (Continued) SYMBOL tS tH tS tH tDD tW tW tW tW tDD tS2 tH2 tS2 tPD5 tPD4 FIGURE 1 1 2 2 1 MIN 20 20 15 5 TYP 23 MAX 80 UNITS ns ns ns ns ns
PARAMETER NRZ-Data In to CLK ENC Data Setup Time Data Hold Time AIN, BIN to CLK DEC Data Setup Time Data Hold Time CLK ENC to OUT1, OUT2 OUT1, OUT2 Pulse Width (CLK ENC Duty Cycle = 50%) fCL = 1.544MHz fCL = 2.048MHz fCL = 6.3212MHz fCL = 8.448MHz CLK DEC to NRZ-Data Out Setup Time CLK DEC to Reset AlS Hold Time of Reset AlS = `0' Setup Time Reset AlS = `1' to CLK DEC Reset AlS to AIS output CLK DEC to Error output
1 1 1 1 2 3 3 3 3 3
35 20 0 -
324 224 79 58 25 -
54 42 62
ns ns ns ns ns ns ns ns ns ns
Pin Descriptions
PIN NUMBER 1 2, 5 FUNCTION Force AIS Mode Select 1, Mode Select 2 DESCRIPTION Pin 19 must be at logic `0' to enable this pin. A logic `1' on this pin forces OUT1 and OUT2 to all `1's. A logic `0' on this pin allows normal operation. MS1 0 0 1 1 MS2 0 1 0 1 Functions As AMI B8ZS B6ZS HDB3
3 4 6 7 8, 9
NRZ Data In CLK ENC NRZ Data Out CLK DEC Reset AIS, AlS
Input data to be encoded into ternary form. The data is clocked by the negative going edge of CLK ENC. Clock encoder, clock for encoding data at NRZ Data In. Decoded data from ternary inputs AIN and BIN. Clock decoder, clock for decoding ternary data on inputs AIN and BIN. Logic `0' on Reset AIS resets a decoded zero counter and either resets AIS output to zero provided 3 or more zeros have been decoded in the preceding Reset AIS period or sets AlS to `1' if less than 3 zeros have been decoded in the preceding two Reset AlS periods. A period of Reset AlS is defined from the bit following the bit during which Reset AlS makes a high to low transition to the bit during which Reset AIS makes the next high to low transition. Ground reference. A logic `1' indicates that a violation of the line coding scheme has been decoded. "OR" function of AIN and BIN for clock regeneration when pin 14 is at logic `0', "OR" function of OUT1 and OUT2 when pin 14 is at logic `1'. Inputs representing the received PCM signal. AIN = `1' represents a positive going `1' and BIN = `1' represents a negative going `1'. AIN and BIN are sampled by the positive going edge of CLK DEC. AIN and BIN may be interchanged.
10 11 12 13, 15
VSS Error Clock AIN, BIN
71
HC-5560 Pin Descriptions
PIN NUMBER 14 (Continued) DESCRIPTION Loop Test Enable, this pin selects between normal and loop back operation. A logic `0' selects normal operation where encode and decode are independent and asynchronous. A logic `1' selects a loop back condition where OUT1 is internally connected to AIN and OUT2 is internally connected to BIN. A decode clock must be supplied. Outputs representing the ternary encoded NRZ Data In signal for line transmission. OUT1 and OUT2 are in return to zero form and are clocked out on the positive going edge of CLK ENC. The length of OUT1 and OUT2 is set by the length of the positive clock pulse. A logic `0' on this pin resets all internal registers to zero. A logic `1' allows normal operation of all internal registers. A logic `1' on this pin forces outputs OUT1 and OUT2 to zero. A logic `0' allows normal operation. Power to chip.
FUNCTION LTE
16, 17
OUT1, OUT2
18 19 20
Reset Output Enable VDD
Functional Description
The HC-5560 TRANSCODER can be divided into six sections: transmission (coding), reception (decoding), error detection, all ones detection, testing functions, and output controls. The transmitter codes a non-return to zero (NRZ) binary unipolar input signal (NRZ Data In) into two binary unipolar return to zero (RZ) output signals (OUT1, OUT2). These output signals represent the NRZ data stream modified according to the selected encoding scheme (i.e., AMl, B8ZS, B6ZS, HDB3) and are externally mixed together (usually via a transistor or transformer network) to create a ternary bipolar signal for driving transmission lines. The receiver accepts as its input the ternary data from the transmission line that has been externally split into two binary unipolar return to zero signals (AIN and BIN). These signals are decoded, according to the rules of the selected line code into one binary unipolar NRZ output signal (NRz Data Out). The encoder and decoder sections of the chip perform independently (excluding loopback condition) and may operate simultaneously. The Error output signal is active high for one cycle of CLK DEC upon the detection of any bipolar violation in the received AIN and BIN signals that is not part of the selected line coding scheme. The bipolar violation is not removed, however, and shows up as a pulse in the NRZ Data Out signal. In addition, the Error output signal monitors the received AIN and BIN signals for a string of zeros that violates the maximum consecutive zeros allowed for the selected line coding scheme (i.e., 15 for AMI, 8 for B8ZS, 6 for B6ZS, and 4 for HDB3). ln the event that an excessive amount of zeros is detected, the Error output signal will be active high for one cycle of CLK DEC during the zero that exceeds the maximum number. In the case that a high level should simultaneously appear on both received input signals AIN and BIN a logical one is assumed and appears on the NRZ Data Out stream with the Error output active. An input signal received at inputs AIN and BIN that consists of all ones (or marks) is detected and signaled by a high
level at the Alarm Indication Signal (AlS) output. This is also known as Blue Code. The AlS output is set to a high level when less than three zeros are received during one period of Reset AIS immediately followed by another period of Reset AlS containing less than three zeros. The AIS output is reset to a low level upon the first period of Reset AlS containing 3 or more zeros. A logic high level on LTE enables a loopback condition where OUT1 is internally connected to AIN and OUT2 is internally connected to BIN (this disables inputs AIN and BIN to external signals). In this condition, NRZ Data In appears at NRZ Data Out (delayed by the amount of clock cycles it takes to encode and decode the selected line code). A decode clock must be supplied for this operation. The output controls are Output Enable and Force AlS. These pins allow normal operation, force OUT1 and OUT2 to zero, or force OUT1 and OUT2 to output all ones (AIS condition).
Line Code Descriptions
AMl, Alternate Mark Inversion, is used primarily in North American T1 (1.544MHz) and T1C (3.152MHz) carriers. Zeros are coded as the absence of a pulse and ones are coded alternately as positive or negative pulses. This type of coding reduces the average voltage level to zero to eliminate DC spectral components, thereby eliminating DC wander. To simplify timing recovery, logic 1's are encoded with 50% duty cycle pulses. e.g.,
PCM CODE 0 0 0 1 01 1 1 01 0 0 00 01
AMI CODE
To facilitate timing maintenance at regenerative repeaters along a transmission path, a minimum pulse density of logic 1s is required. Using AMl, there is a possibility of long strings of zeros and the required density may not always exist, leading to timing jitter and therefore higher error rates. A method for insuring minimum logic 1 density by substituting bipolar code in place of strings of 0s is called BNZS or Bipolar
72
HC-5560
with N Zero Substitution. B6ZS is used commonly in North American T2 (6.3212MHz) carriers. For every string of 6 zeros, bipolar code is substituted according to the following rule: If the immediate preceding pulse is of (-) polarity, then code each group of 6 zeros as 0+- 0+-, and if the immediate preceding pulse is of (+) polarity, code each group of 6 zeros as 0+- 0-+. One can see the consecutive logic 1 pulses of the same polarity violate the AMI coding scheme. e.g.,
6 PCM CODE 0 0 0 1 0 11100 0 B6ZS (-) V V 0 B6ZS (+) V V V = VIOLATION + HDB3 (+) V 0 0 0 + 0 1 HDB3 (-) 00 0
1. If the polarity of the immediate preceding pulse is (-) and there have been an odd (even) number of logic 1 pulses since the last substitution, each group of 4 consecutive zeros is coded as 000-(+00+). 2. If the polarity of the immediate preceding pulse is (+) then the substitution is 000+(-00-) for odd (even) number of logic 1 pulses since the last substitution. e.g.,
4 PCM CODE 0000101 11 00 4 00 0 01
V
+00+
-
+0
0 0 0 +
V
-
0
0
V
-
0
-
+ V = VIOLATION
The 3 in HDB3 refers to the coding format that precludes strings of zeros greater than 3. Note that violations are produced only in the fourth bit location of the substitution code and that successive substitutions produce alternate polarity violations.
B8ZS is used commonly in North American T1 (1.544MHz) and T1C (3.152MHz) carriers. For every string of 8 zeros, bipolar code is substituted according to the following rules: 1. If the immediate preceding pulse is of (-) polarity, then code each group of 8 zeros as 000-+ 0+-. 2. If the immediate preceding pulse is of (+) polarity then code each group of 8 zeros as 000+-0-+. e.g.,
8
PCM CODE
1 0 10 0
0 0
0 0
0
0
0
0 +
0
1
1
0
V
+0
-
B8ZS (-)
V
0 B8ZS (+)
0
0
+
-
0
-
+
V V = VIOLATION
The BNZS coding schemes, in addition to eliminating DC wander, minimize timing jitter and allow a line error monitoring capability. Another coding scheme is HDB3, high density bipolar 3, used primarily in Europe for 2.048MHz and 8.448MHz carriers. This code is similar to BNZS in that it substitutes bipolar code for 4 consecutive zeros according to the following rule:
73
HC-5560 Application Diagram
5V
VDD FROM CODEC OR TRANSCODER ENCODER CLOCK NRZ DATA IN ENCODER CLK ENC OUT2 OUT1 V+ T1, T2, T1C, PCM 30 LINE OUTPUT
FORCE AIS LTE RESET OUTPUT ENABLE CONTROL
MS1 MS2 CLOCK RESET AIS AIS ERROR
MODE SELECT LOGIC INPUTS CLOCK RECOVERY ALARM CLOCK ALARM ERROR ERROR MONITORS
LINE INPUT
DIFF AMP V+

AIN
DECODER NRZ DATA OUT TO CODED OR TRANSCODER MS1 0 0 1 1 MS2 0 1 0 1 SELECTS AMI B8ZS B6ZS HDB3
BIN CLK DEC VSS
DECODER CLOCK
Timing Waveforms
1 fCL tRCL tFCL 90% 50% CLK ENC 10% tS NRZ DATA IN 50% tH 50%
tDD 50% OUT 1, OUT 2 tW 50%
FIGURE 1. TRANSMITTER (CODER) TIMING WAVEFORMS
74
HC-5560 Timing Waveforms
(Continued)
1 fCL tFCL CLK DEC 10% tS 50% AIN, BIN 90% 50% tH tRCL
50% CLOCK tDD 50% NRZ DATA OUT
FIGURE 2. RECEIVER (DECODER) TIMING WAVEFORMS
50% CLK DEC tH2 RESET AIS tS2 50% tPD5 50% tS2
50%
AIS OUTPUT tPD4
50%
ERROR OUTPUT
50%
FIGURE 3. RESET AIS INPUT, AIS OUTPUT, ERROR OUTPUT
CLK DEC RESET AIS NRZ DATA OUT AIS
FIGURE 4.
Two consecutive periods of Reset AIS, each containing less than three zeros, sets AIS to a logic `1' and remains in a logic `1' state until a period of Reset AIS contains three or more zeros.
75
HC-5560 Timing Waveforms
(Continued)
CLK DEC RESET AIS NRZ DATA OUT AIS
FIGURE 5.
Zeros which occur during a high to low transition of Reset AIS are counted with the zeros that occurred before the high to low transition.
NRZ DATA IN CLK ENC OUT 1 AMI OUT 2
OUT 1 HDB3 OUT 2
S S
S
S S
OUT 1 B6ZS OUT 2
S
S
S
S
OUT 1 B8ZS OUT 2 3 1/2 CYCLES 5 1/2 CYCLES
S
S
S
FIGURE 6. ENCODE TIMING AND DELAY
Data is clocked on the negative edge of CLK ENC and appears on OUT1 and OUT2. OUT1 and OUT2 are interchangeable. Bipolar violations and all other pulses inserted by the line coding scheme to encode strings of zeros are labeled with an "S".
76
HC-5560 Timing Waveforms
CLK DEC AMI AIN BIN NRZ DATA OUT
(Continued)
HDB3
AIN BIN
S
S S S
S
S S S
NRZ DATA OUT S S S S S S S S S S
B6ZS
AIN BIN
NRZ DATA OUT
B8ZS
AIN BIN
S S S
S
S S S
S
NRZ DATA OUT
4 CYCLES 6 CYCLES 8 CYCLES
FIGURE 7. DECODE TIMING AND DELAY
Data that appears on AIN and BIN is clocked by the positive edge of CLK DEC, decoded, and zeros are inserted for all valid line code substitutions. The data then appears in non-return to zero to zero form at output NRZ Data Out. AIN and BIN are interchangeable.
CLK DEC E E E S S S S
AIN BIN NRZ DATA OUT ERROR
FIGURE 8.
The ERROR signal indicates bipolar violations that are not part of a valid substitution.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
77

▲Up To Search▲

Price & Availability of HC3-5560-5

	To Download HC3-5560-5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .